首页> 外国专利> DESIGN METHOD OF INTEGRATED CIRCUIT DEVICE, DESIGN SUPPORT SYSTEM OF INTEGRATED CIRCUIT DEVICE, DESIGN SUPPORT PROGRAM OF INTEGRATED CIRCUIT DEVICE, MACROCELL, INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC APPARATUS

DESIGN METHOD OF INTEGRATED CIRCUIT DEVICE, DESIGN SUPPORT SYSTEM OF INTEGRATED CIRCUIT DEVICE, DESIGN SUPPORT PROGRAM OF INTEGRATED CIRCUIT DEVICE, MACROCELL, INTEGRATED CIRCUIT DEVICE, AND ELECTRONIC APPARATUS

机译:集成电路设备的设计方法,集成电路设备的设计支持系统,集成电路设备的设计支持程序,宏单元,集成电路设备和电子设备

摘要

PROBLEM TO BE SOLVED: To provide a design method of an integrated circuit device capable of reducing characteristic variation of a macrocell due to the difference of an automatic generation part of a dummy pattern for a flattening process of an insulation layer surface; and the like.;SOLUTION: This design method of an integrated circuit device includes: a step (step S10) of arranging and wiring a macrocell having the dummy pattern for a surface flattening process formed thereon, and including layout information, in at least one wiring layer, based on circuit connection information of the integrated circuit device; a step (step S14) of detecting a region capable of arranging a predetermined dummy pattern for the surface flattening process based on the layout information of the integrated circuit device after the arrangement and wiring; and a step (step S16) of generating a dummy pattern in the region.;COPYRIGHT: (C)2009,JPO&INPIT
机译:解决的问题:提供一种集成电路装置的设计方法,其能够减少由于用于绝缘层表面的平坦化处理的虚设图案的自动产生部分的差异而导致的宏单元的特性变化;解决方案:该集成电路器件的设计方法包括:在至少一个中布置并布线其上形成有用于表面平坦化处理的哑图案并包括布局信息的宏单元的步骤(步骤S10)。布线层,基于集成电路装置的电路连接信息;步骤(步骤S14),其根据布置和布线之后的集成电路器件的布局信息,检测能够布置用于表面平坦化处理的预定虚拟图案的区域; COPYRIGHT:(C)2009,JPO&INPIT;以及在该区域中生成虚拟图案的步骤(步骤S16)。

著录项

  • 公开/公告号JP2009076766A

    专利类型

  • 公开/公告日2009-04-09

    原文格式PDF

  • 申请/专利权人 SEIKO EPSON CORP;

    申请/专利号JP20070245744

  • 发明设计人 KUWANO SHUNICHI;

    申请日2007-09-21

  • 分类号H01L21/82;H01L21/822;H01L27/04;H01L21/3205;H01L23/52;G06F17/50;

  • 国家 JP

  • 入库时间 2022-08-21 19:41:47

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