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GROB ADJUSTABLE DELAYING CIRCUITS WITH FLANK SUPPRESSION CIRCUITS IN DELAYING RULES
GROB ADJUSTABLE DELAYING CIRCUITS WITH FLANK SUPPRESSION CIRCUITS IN DELAYING RULES
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机译:延迟规则中带有侧翼抑制电路的GROB可调延迟电路
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摘要
The invention discloses a delay locked loop which includes a coarse delay tuner circuit with edge suppressors suitable for use with delay locked loops (DLLs). The disclosed tuner circuit provides reduced lock time of the DLL circuit.
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