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Decision feedback equalizer coupled with both a parallel processing as well as processing with perspectives
Decision feedback equalizer coupled with both a parallel processing as well as processing with perspectives
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机译：决策反馈均衡器与并行处理以及透视处理相结合
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摘要
A method and apparatus are disclosed for increasing the effective processing speed of a parallel decision-feedback equalizer (DFE) by combining block processing and look-ahead techniques in the selection (multiplexing) stage. The present invention extends a parallel DFE by using look-ahead techniques in the selection stage to precompute the effect of previous blocks on each subsequent block, and to thereby remove the serial output dependency. The parallel DFE includes a multiplexor tree structure that selects an appropriate output value for each block and precomputes the effect of previous blocks on each subsequent block. A multiplexing delay algorithm on the order of logN is employed to resolve the output dependency and thus speeds up parallel block processing DFEs. The disclosed DFE architecture can be combined with pipelining to completely eliminate the critical path problem. Pipelining reduces the required critical path timing to one multiplexing time. The disclosed multiplexor tree circuitry for the parallel DFE groups multiplexor blocks into groups of two, referred to as block pairs, and provides at least one multiplexor for each block, i, to select an output value, yi, from among the possible precomputed values. The output of each parallel block depends on the possible precomputed values generated by the look-ahead processors for the block, as well as the actual values that are ultimately selected for each previous block. In order to reduce the delay in obtaining each actual output value, the present invention assumes that each block contains each possible value, and carries the assumption through to all subsequent blocks. Thus, the number of multiplexors required to select from among the possible values grows according to N·logN, where N is the block number.
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机译：公开了一种用于通过在选择（复用）阶段中组合块处理和预见技术来提高并行判决反馈均衡器（DFE）的有效处理速度的方法和装置。本发明通过在选择阶段中使用先行技术来扩展并行DFE，以预先计算先前的块对每个后续块的影响，从而消除串行输出依赖性。并行DFE包括一个多路复用器树结构，该结构为每个块选择适当的输出值，并预先计算先前的块对每个后续块的影响。采用logN顺序的多路复用延迟算法来解决输出依赖性，从而加快并行块处理DFE的速度。所公开的DFE架构可以与流水线结合以完全消除关键路径问题。流水线将所需的关键路径时序减少到一个多路复用时间。所公开的用于并行DFE的多路复用器树电路将多路复用器块分为两组，称为块对，并为每个块i提供至少一个多路复用器，以选择输出值y i ，从可能的预先计算的值中。每个并行块的输出取决于前瞻处理器为该块生成的可能的预先计算的值，以及最终为每个先前的块选择的实际值。为了减少获得每个实际输出值的延迟，本发明假定每个块包含每个可能的值，并将该假设传递到所有随后的块。因此，从可能值中进行选择所需的多路复用器的数量根据N×logN而增加，其中N是块数。
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