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Efficient Verification Apparatus in ESL Design Methodology, and the Verification Method Using the Same
Efficient Verification Apparatus in ESL Design Methodology, and the Verification Method Using the Same
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机译：ESL设计方法论中的有效验证装置以及使用该方法的验证方法
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摘要
The present invention for the design of the design verification of the digital system from the extremely complex systems and relates to a systemic level designed systematic and efficient verification method and a verification device using the same to efficiently performed. ; In the present invention, to cause the verification software of the present invention which is carried out at any computer add one or more additional code or additional circuitry in the design object in the DUV naejineun DUV, and has one or more in the DUV entire naejineun DUV when necessary design object implement of original design code model or more design objects 1 in the DUV by the modeling process through an automated way or passive manner using the validation software of the present invention to the other codes high level of abstraction for the hardware-based verification platform or DUV by implementing the modeling process and the other one or more design objects in the DUV for the one or more design objects in a hardware-based platform and to perform the verification using one or more simulations. Performing simulations is more than more than one simulation is performed on one or more computers 1 simulator or 1 simulator and one or more hardware-based verification platform performed, or two or more simulators or two or more simulators running on two or more computers connected over a network by using the and it is 1 using the more hardware-based verification platform and enabling the widespread reduction in overall verification time and the verification cost by enabling also performed in parallel, able to greatly improve the efficiency of verification. ; Hardware Verification
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