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PIPELINED PROCESSOR AND COMPILER/SCHEDULER FOR VARIABLE NUMBER BRANCH DELAY SLOTS
PIPELINED PROCESSOR AND COMPILER/SCHEDULER FOR VARIABLE NUMBER BRANCH DELAY SLOTS
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机译：可变数目分支延迟槽的流水线处理器和编译器/调度器
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摘要
Different numbers of delay slots are assigned by a compiler/scheduler to each different type of jump operation in a pipelined processor system. The number of delay slots is variable and kept to the minimum needed by each type of jump operation. A compatible processor uses a corresponding number of branch delay slots to exploit the difference in predictability of different types of branch or jump operations. Different types of jump operations resolved their target addresses in different numbers of delay slots. As a result, the compiler/scheduler is able to generate more efficient code than for a processor with a fixed number of delay slots for all jump types, resulting in better processor performance.
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