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Innovated technique to reduce memory interface write mode SSN in FPGA
Innovated technique to reduce memory interface write mode SSN in FPGA
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机译：减少FPGA中存储器接口写模式SSN的创新技术
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摘要
The amount of simultaneous switching noise generated through the operation of a programmable device can be reduced by reducing the number of pins switching at the same time. An I/O bank can include a number of I/O pin subsets, or DQS groups, each programmed to switch at a different time so that the switching times of the various pins can be staggered for each system clock cycle. Programmable delay elements can be used to control the delay of each subset. The programmable elements can be placed between the system clock and the output registers in order to delay the receiving of the clock signal by the registers and therefore delaying the switching of the output buffers. The programmable delay elements also can be placed between the output registers and the output buffers in order to delay the receiving of the output data by, and subsequent switching of, the output buffers.
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机译：通过减少同时开关的引脚数，可以减少通过可编程设备的操作而产生的同时开关噪声的数量。一个I / O bank可以包括多个I / O引脚子集或DQS组，每个子集或DQS组被编程为在不同的时间进行切换，以便可以针对每个系统时钟周期错开各个引脚的切换时间。可编程延迟元件可用于控制每个子集的延迟。可编程元件可以放置在系统时钟和输出寄存器之间，以延迟寄存器对时钟信号的接收，从而延迟输出缓冲器的切换。可编程延迟元件也可以放置在输出寄存器和输出缓冲器之间，以便通过输出缓冲器以及随后的输出缓冲器的切换来延迟输出数据的接收。
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