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Structure and method for measuring the channel boosting voltage of NAND flash memory at a node between drain/source select transistor and adjacent flash memory cell
Structure and method for measuring the channel boosting voltage of NAND flash memory at a node between drain/source select transistor and adjacent flash memory cell
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机译：在漏极/源极选择晶体管与相邻闪存单元之间的节点处测量NAND闪存的沟道升压电压的结构和方法
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摘要
Provided is a structure for testing a NAND flash memory including a string select transistor, a source select transistor, flash memory cells connected in series between the string select transistor and a source select transistor and a measurement pad coupled to a node between a flash memory cell and the string select transistor or the source select transistor.
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