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Hierarchical stochastic analysis process optimization for integrated circuit design and manufacture
Hierarchical stochastic analysis process optimization for integrated circuit design and manufacture
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机译：集成电路设计和制造的分层随机分析过程优化
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摘要
An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces the large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance metrics to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). A hierarchical SAP process breaks an overall circuit into a plurality of subcircuits and performs circuit simulation and SAP analysis steps on each subcircuit. An integration and reduction process combines the analysis results of each subcircuit, and a final SPICE/SAP process provides a model for the overall circuit based on the subcircuits.
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