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DOUBLE-EDGE TRIGGERED SCANNABLE PULSED FLIP-FLOP FOR HIGH FREQUENCY AND/OR LOW POWER APPLICATIONS
DOUBLE-EDGE TRIGGERED SCANNABLE PULSED FLIP-FLOP FOR HIGH FREQUENCY AND/OR LOW POWER APPLICATIONS
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机译：适用于高频和/或低功耗应用的双边触发可缩放脉冲翻转器
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摘要
A circuit for data storage is presented. The circuit includes clock generation circuits for generating a pulse clock signal having first and second clock pulses for each clock cycle of a system clock and first and second scan clock signals. The circuit further includes a scannable pulse flip-flop circuit having a data input and a data output that are connected with an internal storage node, and a scan input and a scan output that are also connected with the internal storage node. In a function mode of operation, the first and second scan clock signals are held at a logic level to allow data to pass from the data input to the internal storage node at the first clock pulse and from the internal storage node to the data output at the second clock pulse signal. In a scan mode of operation the pulse clock signal is held at a logic level to allow data to pass from the scan input to the internal storage node at a pulse of the first scan clock signal and from the internal storage node to the scan output at a pulse of the second scan clock signal.
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