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TIMING CONSTRAINT-GENERATING SYSTEM OF LOGIC CIRCUIT AND TIMING CONSTRAINT-GENERATING METHOD OF LOGIC CIRCUIT, CONTROL PROGRAM, AND READABLE RECORDING MEDIUM
TIMING CONSTRAINT-GENERATING SYSTEM OF LOGIC CIRCUIT AND TIMING CONSTRAINT-GENERATING METHOD OF LOGIC CIRCUIT, CONTROL PROGRAM, AND READABLE RECORDING MEDIUM
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机译：逻辑电路的时序约束生成系统以及逻辑电路的时序约束生成方法，控制程序和可读记录介质
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摘要
PROBLEM TO BE SOLVED: To shorten processing time in an integrated circuit-designing flow and extract only a timing exception which effectively improves a result of logic synthesis.;SOLUTION: A logic synthesizable hardware description 21, in which a designing-target integrated circuit is expressed, and clock specifications 22 for correlating clock circuits with circuit data are input, and timing exceptions are extracted by using them. A part of target circuits in which the timing exceptions are extracted is selected by a circuit-selecting means 13 so that generating conditions 23 is satisfied, and a part of the extracted timing exceptions is selected by a timing constraint-selecting means 15. Only timing exceptions are extracted, which have high improvement effect to designing/verifying tools such as logic synthesis tools, automatic placing and routing tools and static timing analyses, which conduct designing and verification with timing constraint, as a base, which is input according to the generating conditions 23. Then, things which have possibility of deteriorating the quality of the design are excluded from the extracted timing exceptions.;COPYRIGHT: (C)2008,JPO&INPIT
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