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CHIP SCALE PACKAGE, CMOS IMAGE SCALE PACKAGE, AND MANUFACTURING METHOD OF CMOS IMAGE SCALE PACKAGE
CHIP SCALE PACKAGE, CMOS IMAGE SCALE PACKAGE, AND MANUFACTURING METHOD OF CMOS IMAGE SCALE PACKAGE
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机译：芯片规模封装，CMOS图像规模封装以及CMOS图像规模封装的制造方法
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摘要
PROBLEM TO BE SOLVED: To provide an isolation structure of a chip scale package of a CMOS image sensor device, and to provide its manufacturing method.;SOLUTION: The chip scale package of the CMOS image sensor includes a transparent substrate 110 used as a support structure of a package. The transparent substrate 110 has a first cut end face 105a and a second cut end face 105b. A CMOS image sensor die 120 having a die circuit is mounted on the transparent substrate 110, and sealing material 130 is mounted on the substrate so that the CMOS image sensor die 120 is sealed. Connection wiring is extended from the die circuit to two or more contact terminals of the chip scale package on the sealing material 130. The connection wiring is exposed from the first cut end face 105a. The insulator is mounted on the first cut end face 105a so that the exposed connection wiring is protected and the same plane face as the second cut end face 105b is formed.;COPYRIGHT: (C)2008,JPO&INPIT
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