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LOGIC VERIFICATION SUPPORT PROGRAM, RECORDING MEDIUM WITH THE PROGRAM RECORDED, LOGIC VERIFICATION SUPPORT APPARATUS, AND LOGIC VERIFICATION SUPPORT METHOD

机译：逻辑验证支持程序，使用记录的程序记录介质，逻辑验证支持设备和逻辑验证支持方法

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摘要

PPROBLEM TO BE SOLVED: To shorten the period of logic verification by presenting error messages easy for designers to understand. PSOLUTION: Character strings each enumerating, in transition order, character strings meaning transition conditions for transition branches followed from an initial state to each transition state are extracted from a finite state machine model of a hardware module M to be verified, and the enumerating character strings are each embedded in an embedding position in a modifying character string modifying a character string representing each state of the finite state machine model, to create message information 810 meaning the transitions followed from the initial state to each transition state. The message information 810 becomes an output. PCOPYRIGHT: (C)2009,JPO&INPIT

机译：

要解决的问题：通过提供易于设计人员理解的错误消息来缩短逻辑验证的时间。

解决方案：分别从转换顺序中枚举表示从初始状态到每个转换状态的转换分支转换条件的字符串，这些字符串是从要验证的硬件模块M的有限状态机模型中提取的，将枚举字符串分别嵌入在修改字符串中的嵌入位置中，该修改字符串对表示有限状态机模型的每个状态的字符串进行修改，以创建消息信息810，该消息信息810表示从初始状态到每个过渡状态的过渡。消息信息810成为输出。

版权：（C）2009，日本特许厅＆INPIT 展开▼

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公开/公告号JP2008250504A

专利类型
公开/公告日2008-10-16

原文格式PDF
申请/专利权人 FUJITSU LTD;
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申请/专利号JP20070089143
发明设计人 IWASHITA HIROAKI;
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申请日2007-03-29
分类号G06F17/50;
国家 JP
入库时间 2022-08-21 20:25:07

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