首页> 外国专利> Method for handling errors with examination of concept of integrated circuit, involves examining concept of integrated circuit on basis of preset rules for errors, where concept comprises several cells

Method for handling errors with examination of concept of integrated circuit, involves examining concept of integrated circuit on basis of preset rules for errors, where concept comprises several cells

机译:通过检查集成电路的概念来处理错误的方法,包括基于预设的错误规则来检查集成电路的概念,其中概念包括多个单元

摘要

The method involves examining concept of integrated circuit on basis of preset rules for errors, where the concept comprises several cells. The permitted error with indication of the cell in the masking file is stored, in which the error arises, and an error is identified if concept is deviated from the preset rules. The error is registered in error file, and identified error is registered in masking file.
机译:该方法包括基于用于错误的预设规则来检查集成电路的概念,其中该概念包括几个单元。在掩码文件中存储有指示单元的允许错误,其中会出现错误,并且如果概念与预设规则有所不同,则会识别出错误。错误记录在错误文件中,识别出的错误记录在屏蔽文件中。

著录项

  • 公开/公告号DE102006006782A1

    专利类型

  • 公开/公告日2007-08-23

    原文格式PDF

  • 申请/专利权人 INFINEON TECHNOLOGIES AG;

    申请/专利号DE20061006782

  • 发明设计人 HOFSAESS MARKUS;

    申请日2006-02-14

  • 分类号H01L21/822;G06F17/50;

  • 国家 DE

  • 入库时间 2022-08-21 20:29:24

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