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A METHOD FOR TESTING A MEMORY ARRAY AND A MEMORY-BASED DEVICE SO TESTABLE WITH A FAULT RESPONSE SIGNALIZING MODE FOR WHEN FINDING PREDETERMINED CORRESPONDENCE BETWEEN FAULT PATTERNS SIGNALIZING ONE SUCH FAULT PATTERN ONLY IN THE FORM OF A COMPRESSED RESPONSE
A METHOD FOR TESTING A MEMORY ARRAY AND A MEMORY-BASED DEVICE SO TESTABLE WITH A FAULT RESPONSE SIGNALIZING MODE FOR WHEN FINDING PREDETERMINED CORRESPONDENCE BETWEEN FAULT PATTERNS SIGNALIZING ONE SUCH FAULT PATTERN ONLY IN THE FORM OF A COMPRESSED RESPONSE
A memory array, and in particular, an embedded memory array is tested by interfacing to a stimulus generator and a response evaluator pair. In a non-test condition the pair is steered in a transparent mode, and in a test condition in a stimulus generating mode and a response evaluating mode respectively. In a subsequent array repair condition row and/or column-based repair intervention are allowed. In particular, the evaluator will evaluate correspondence between successive fault patterns, and further in a fault response signalizing mode to external circuitry on the basis of a predetermined correspondence between an earlier fault pattern and a later fault pattern signalize one of the two compared patterns only in the form of a lossless compressed response pattern.
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