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A CLOCK DESIGN METHOD FOR LOW-POWER RTL DESIGN AND A CLOCK FOR LOW-POWER RTL DESIGN
A CLOCK DESIGN METHOD FOR LOW-POWER RTL DESIGN AND A CLOCK FOR LOW-POWER RTL DESIGN
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机译：低功耗RTL设计的时钟设计方法和低功耗RTL设计的时钟
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摘要
A clock design method for low-power RTL(Resistor-Transistor Logic) design and a clock for low-power RTL design are provided to reduce the number of clocks inputted into a flip-flop configuring a register, thereby reducing power consumption due to unnecessary clocks, improving the maximum operation frequency and reducing a design area. A clock design method for low-power RTL(Resistor-Transistor Logic) design comprises the following steps of: inputting an external input signal and a clock signal into a clock gating block(11); generating a salve clock signal from the clock gating block and outputting the generating slave clock signal; and controlling operations of a register(12) by inputting the slave clock signal into the register.
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