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PROCESSOR CORE AND METHOD FOR MANAGING BRANCH MISPREDICTION IN AN OUT-OF-ORDER PROCESSOR PIPELINE
PROCESSOR CORE AND METHOD FOR MANAGING BRANCH MISPREDICTION IN AN OUT-OF-ORDER PROCESSOR PIPELINE
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机译：处理顺序管道中分支错误的处理器核心和方法
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摘要
A processor core and method for managing branch misprediction in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control logic. Operation of the instruction fetch portion is decoupled from operation of the instruction execution portion. Following detection of a control transfer misprediction, operation of the instruction fetch portion is halted and instructions residing in the instruction fetch portion are invalidated. When the instruction associated with the misprediction reaches a selected pipeline stage, instructions residing in the instruction execution portion of the pipeline are invalidated and the flow of instructions from the instruction fetch portion to the instruction execution portion of the processor pipeline is restarted. A mispredict instruction identification checker and instruction identification tags are used to determine if a control transfer instruction is permitted to redirect instruction fetching.
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