A parallel-prefix modulo 2n−1 adder that is as fast as the fastest parallel prefix 2n integer adders, does not require an extra level of logic to generate the carry values, and has a very regular structure to which pipeline registers can easily be added. All nodes of the adder have a fanout ≦2. In the prefix structure of the adder, each carry value term output by the parallel prefix structure is determined by the all of the bits in the operands input to the adder. In one embodiment, there are log2 n stages in the prefix structure. Each stage has n logical operators, and all of the logical operators in the prefix structure are of the same kind. Pipeline registers may be inserted before and/or after a stage in the prefix structure.
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机译：与最快的并行前缀2 n 整数加法器一样快的并行前缀模2 n −1加法器，不需要额外的逻辑来生成进位值，并且具有非常规则的结构，可以轻松地向其中添加流水线寄存器。加法器的所有节点的扇出度≤2。在加法器的前缀结构中，并行前缀结构输出的每个进位值项由输入到加法器的操作数中的所有位确定。在一实施例中，前缀结构中有log 2 n个阶段。每个阶段都有n个逻辑运算符，并且前缀结构中的所有逻辑运算符都是相同的。可以在前缀结构中的阶段之前和/或之后插入流水线寄存器。
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