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Method and device to reduce gate-induced drain leakage (GIDL) current in thin gate oxides MOSFETs

机译:减少薄栅氧化物MOSFET中的栅感应漏极泄漏电流的方法和装置

摘要

An integrated circuit which provides a FET device having reduced GIDL current is described. A semiconductor substrate is provided wherein active regions are separated by an isolation region and a gate oxide layer is provided on the active regions. A gate electrode is provided upon the gate oxide layer wherein beneath an edge of the gate electrode, a gate-drain overlap region having a high dose ion implant is provided.
机译:描述了提供具有减小的GIDL电流的FET器件的集成电路。提供了一种半导体衬底,其中有源区被隔离区隔开,并且栅氧化物层设置在有源区上。在栅氧化物层上提供栅电极,其中在栅电极的边缘下方,提供具有高剂量离子注入的栅漏重叠区。

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