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Vertical junction field effect transistors, and methods of producing the vertical junction field effect transistors

机译:垂直结场效应晶体管,以及制造垂直结场效应晶体管的方法

摘要

A vertical JFET 1a according to the present invention has an n+ type drain semiconductor portion 2, an n-type drift semiconductor portion 3, a p+ type gate semiconductor portion 4, an n-type channel semiconductor portion 5, an n+ type source semiconductor portion 7, and a p+ type gate semiconductor portion 8. The n-type drift semiconductor portion 3 is placed on a principal surface of the n+ type drain semiconductor portion 2 and has first to fourth regions 3a to 3d extending in a direction intersecting with the principal surface. The p+ type gate semiconductor portion 4 is placed on the first to third regions 3a to 3c of the n-type drift semiconductor portion 3. The n-type channel semiconductor portion 5 is placed along the p+ type gate semiconductor portion 4 and is electrically connected to the fourth region 3d of the n-type drift semiconductor portion 3.
机译:根据本发明的垂直JFET 1 a 具有n + 型漏极半导体部分 2 ,n型漂移半导体部分 3 ,ap + 型栅极半导体部分 4 ,n型沟道半导体部分 5 ,n + 型源半导体部分 7 和ap + 型栅极半导体部分 8 。 n型漂移半导体部分 3 放置在n + 型漏极半导体部分 2 的主表面上,并具有第一至第四区域 3 a 3 d 沿与主表面相交的方向延伸。 p + 型栅极半导体部分 4 放置在第一至第三区域 3 a n型漂移半导体部分 3 的3 c 。 n型沟道半导体部分 5 沿着p + 型栅极半导体部分 4 放置,并电连接到第四区域 3的> 3 d

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