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Comparing a selected portion of data on a bus with a specified pattern with logic to detect a match and logic to detect logic 1 in any of the designated bits
Comparing a selected portion of data on a bus with a specified pattern with logic to detect a match and logic to detect logic 1 in any of the designated bits
A match circuit (300) connected to a bus (104) carrying data is described. In one embodiment, the match circuit (104) comprises logic (301a, 301b, 301c) for activating a match_mm signal when a selected N-bit portion of the data matches an N-bit threshold for all bits selected by an N-bit match mask ("mmask") and logic (301e, 301f, 301g) for activating a match_OR signal when at least one of one or more designated bits of the selected N-bit portion of the data is a logic 1 or if there are no designated bits.
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