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METHOD AND APPARATUS FOR PHYSICAL BUDGETING DURING RTL FLOORPLANNING

机译:RTL地板规划期间的物理预算编制方法和装置

摘要

A feasible floorplan of a circuit is determined and budgeted in the early phases of circuit design. The process of determining the floorplan and budget includes estimating RTL complexity, physical partitioning, block placement, block i/o placement and top level global routing, and verifying feasibility of the floorplan. Allocation of global timing constraints to each block is performed by producing logic cones representing timing of circuit paths in each block. The circuit paths are optimized to determine a feasible timing for each block. The global constraints are allocated proportionally to each block based on the feasible timing for each block.
机译:在电路设计的早期阶段,确定可行的电路布局图并进行预算。确定平面图和预算的过程包括估算RTL复杂性,物理分区,块放置,块I / O放置和顶层全局路由,以及验证平面图的可行性。通过产生表示每个块中的电路路径的时序的逻辑锥,来向每个块分配全局时序约束。优化电路路径以确定每个模块的可行时序。基于每个块的可行时序,将全局约束按比例分配给每个块。

著录项

  • 公开/公告号EP1330743A4

    专利类型

  • 公开/公告日2005-12-14

    原文格式PDF

  • 申请/专利权人 CADENCE DESIGN SYSTEMS INC.;

    申请/专利号EP20010992956

  • 发明设计人 GINETTI ARNOLD;

    申请日2001-10-30

  • 分类号G06F17/50;

  • 国家 EP

  • 入库时间 2022-08-21 21:33:10

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