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Method of computer-assisted design of integrated circuit chips, and library of delay time values for computer-assisted design of such chips
Method of computer-assisted design of integrated circuit chips, and library of delay time values for computer-assisted design of such chips
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机译：集成电路芯片的计算机辅助设计方法以及用于此类芯片的计算机辅助设计的延迟时间库
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摘要
A method of placing integrated circuit chips on a wafer uses a library of average delay time values of logic gates. Exposure-dependent delay time values of the logic gates, which result from exposure of a unit area to a beam of radiation, are additionally stored in the library. These delay time values are detected by successively exposing unit areas of a test wafer to a beam of radiation as a function of relative positions of each integrated circuit chip within the unit exposure area. In a modified embodiment, only one integrated circuit chip within each unit area is exposed to the radiation beam, and the exposure-dependent delay time values are detected as a function of position within the exposed integrated circuit chip or as a function of distance from the center of the each unit area.
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