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Optimizing locations of pins for blocks in a hierarchical physical design by using physical design information of a prior hierarchical physical design
Optimizing locations of pins for blocks in a hierarchical physical design by using physical design information of a prior hierarchical physical design
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机译：通过使用先前的分层物理设计的物理设计信息来优化分层物理设计中的块的引脚位置
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摘要
Method of optimizing locations of pins for blocks in a hierarchical physical design by using physical design information of a prior hierarchical physical design is provided and described. In one embodiment, a method of determining a plurality of locations of pins for each block of a physical design of a current integrated circuit includes retrieving physical design information from a prior physical design of a prior integrated circuit. The physical design information includes a routing congestion profile. Continuing, a router is provided a plurality of constraints based on the routing congestion profile. Then, the router is used to perform a top-level route for generating locations of pins for each block. Each pin of the block is created at a location where a global route enters the block or a location where a global route exits the block.
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