Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system

• 1. 用于在一个分布式存储器、高速缓存相干的多处理器系统中把有序的输入/输出事务流水线处理到相干存储器的方法和装置 [P] . 中国专利： CN1470019A . 2004-01-21
• 2. 用于流水线处理有序的输入/输出事务的设备、方法和计算机系统 [P] . 中国专利： CN1297903C . 2007.01.31
• 3. Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system [P] . AU8127301A . 2002-03-04

  机译： 用于将有序输入/输出事务流水线化到分布式存储器，高速缓存一致性多处理器系统中的一致性存储器的方法和装置

• 4. METHOD AND APPARATUS FOR PIPELINING ORDERED INPUT/OUTPUT TRANSACTIONS IN A CACHE COHERENT, MULTI-PROCESSOR SYSTEM [P] . 欧洲知识产权局专利： EP1311956B1 . 2011-09-28

  机译： 缓存相干多处理器系统中有序输入/输出事务的方法和设备

• 5. METHOD AND APPARATUS FOR PIPELINING ORDERED INPUT/OUTPUT TRANSACTIONS IN A CACHE COHERENT, MULTI-PROCESSOR SYSTEM [P] . SG95199A1 . 2003-04-23

  机译： 缓存相干多处理器系统中有序输入/输出事务的方法和设备

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