Multi-bank integrated circuit memory devices having high-speed memory access timing
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机译：具有高速存储器访问定时的多组集成电路存储器
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摘要
Integrated circuit memory devices support write and read burst modes of operation with uniformly short interconnect paths that provide high-speed memory access timing characteristics. These memory devices include a semiconductor chip having a memory core therein and at least N bond pads thereon. The memory core is configured to support a xN burst-M write mode of operation at QDR and/or DDR rates, where N is greater than four and M is greater than one. The memory core is further configured to support one-to-one mapping between burst-M write data received at each of the N bond pads and corresponding ones of N memory blocks in the memory core during the xN burst-M write mode of operation.
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