首页> 外国专利> DIGITAL LOGIC TEST METHOD TO SYSTEMATICALLY APPROACH FUNCTIONAL COVERAGE COMPLETELY AND RELATED APPARATUS AND SYSTEM

DIGITAL LOGIC TEST METHOD TO SYSTEMATICALLY APPROACH FUNCTIONAL COVERAGE COMPLETELY AND RELATED APPARATUS AND SYSTEM

机译:系统地完全覆盖功能覆盖的数字逻辑测试方法及相关装置和系统

摘要

A digital logic test method for systematically testing a pipeline-structured integrated circuit chip is disclosed. The method includes the steps of: providing an integrated circuit chip capable of executing a plurality of instructions during a period of time, each of the instructions being executed according to a plurality of sequentially ordered operation segments, sorting the instructions, and designing a plurality of test patterns to test the integrated circuit according to the sorting result and STAGE test segments corresponding to the STAGE operation segments.
机译:公开了一种用于系统地测试流水线结构的集成电路芯片的数字逻辑测试方法。该方法包括以下步骤:提供一种能够在一段时间内执行多个指令的集成电路芯片,每个指令根据多个顺序排序的操作段执行,对指令进行排序,以及设计多个测试图案,以根据排序结果以及对应于STAGE运算段的STAGE测试段测试集成电路。

著录项

  • 公开/公告号US2006161828A1

    专利类型

  • 公开/公告日2006-07-20

    原文格式PDF

  • 申请/专利权人 CHIH-WEN LIN;

    申请/专利号US20050905734

  • 发明设计人 CHIH-WEN LIN;

    申请日2005-01-19

  • 分类号G01R31/28;G06F11/00;

  • 国家 US

  • 入库时间 2022-08-21 21:47:35

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