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Di raemyong synchronous dynamic clock generation circuit
Di raemyong synchronous dynamic clock generation circuit
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机译：迪雷姆勇同步动态时钟发生电路
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摘要
A clock signal generating circuit for use in a synchronous dynamic random access memory device. The clock signal generating circuit includes an input buffer for converting an externally supplied system clock signal having a first voltage level into a clock signal having a voltage level necessary for operating with the internal circuitry of the memory device. An enable path circuit generates a second transition of an internal clock signal which occurs substantially simultaneous the second transition of the system clock signal. The enable path circuit generates the first transition of the internal clock signal after the internal clock signal is maintained at the second state for a predetermined interval responsive to first and second disable signals. Finally, a disable path circuit receives the clock signal generated from the input buffer and supplies the first and second disable signals to the enable path circuit.
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