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METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE TO REDUCE SURFACE ROUGHNESS OF VIA HOLE WITHOUT USING PLANARIZATION PROCESS
METHOD FOR FORMING METAL LINE OF SEMICONDUCTOR DEVICE TO REDUCE SURFACE ROUGHNESS OF VIA HOLE WITHOUT USING PLANARIZATION PROCESS
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机译：不使用平面化工艺而形成用于减小孔的表面粗糙度的半导体装置金属线的方法
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摘要
PURPOSE: A method for forming a metal line of a semiconductor device is provided to reduce surface roughness of a via hole by using a photosensitive polyimide as an interlayer dielectric without planarization processing. CONSTITUTION: An interlayer dielectric(18) made of a photosensitive polyimide is formed on a substrate(10) having a lower metal line. A via hole is formed by patterning the interlayer dielectric. A glue layer(20a) and a metal seed layer are sequentially formed on the resultant structure. A trench is formed using a photoresist pattern(22). By electroplating the metal seed layer, a via and an upper metal line are formed in the via hole and the trench, respectively.
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