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SEMICONDUCTOR MEMORY DEVICE HAVING ADDITIVE LATENCY, ESPECIALLY PREVIOUSLY GENERATING COLUMN SELECTION SIGNAL AND ACTIVATING IT AFTER ACTIVE LATENCY
SEMICONDUCTOR MEMORY DEVICE HAVING ADDITIVE LATENCY, ESPECIALLY PREVIOUSLY GENERATING COLUMN SELECTION SIGNAL AND ACTIVATING IT AFTER ACTIVE LATENCY
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机译：具有附加延迟的半导体存储器，特别是在活动延迟后预先生成列选择信号并激活它的半导体存储器
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摘要
PURPOSE: A semiconductor memory device having additive latency is provided to improve operation speed and thus to reduce data output time after an address is applied. CONSTITUTION: A command decoder(10) generates an internal command signal by decoding an external command. An additive latency ending signal generation unit(41) generates an additive latency ending signal by delaying an output signal of the command decoder corresponding to a read command as much as the time corresponding to additive latency. And a column selection signal generation unit(12) outputs a column selection signal synchronized to the additive latency ending signal by receiving a column address and the output signal of the command decoder corresponding to the read command.
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