首页> 外国专利> METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE CAPABLE OF SUPPRESSING MUTUAL DIFFUSION OF IMPURITIES IN GATE ELECTRODE DISPOSED NEAR BOUNDARY BETWEEN N-CHANNEL TYPE MISFET AND P-CHANNEL TYPE MISFET ADOPTING POLYCIDE DUAL-GATE STRUCTURE, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FABRICATED THEREBY

METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE CAPABLE OF SUPPRESSING MUTUAL DIFFUSION OF IMPURITIES IN GATE ELECTRODE DISPOSED NEAR BOUNDARY BETWEEN N-CHANNEL TYPE MISFET AND P-CHANNEL TYPE MISFET ADOPTING POLYCIDE DUAL-GATE STRUCTURE, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE FABRICATED THEREBY

机译：制造能抑制杂质的扩散的电路集成设备的方法，该杂质可在N通道型MISFET和P通道型MISFET之间采用近似的双晶形结构，并在复合材料中采用双胶结结构，从而抑制杂质的相互扩散。

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PURPOSE: A method of fabricating a semiconductor integrated circuit device and a semiconductor integrated circuit device fabricated thereby are provided to suppress mutual diffusion of impurities in a gate electrode disposed near a boundary between an n-channel type MISFET and a p-channel type MISFET. CONSTITUTION: A gate insulating layer(6a,6b) is formed on a main surface of a semiconductor substrate(1). A silicon layer is formed thereon. A plurality of kinds of impurities are introduced into the silicon layer, and thereby one part of the silicon layer is formed as a n-type silicon layer and the other part is formed as a p-type silicon layer. A conductive layer containing tungsten or tungsten silicide as a main component is formed above each of the n-type silicon layer and the p-type silicon layer. The conductive layer, the n-type silicon layer, and the p-type silicon layer are patterned and thereby a gate electrode(10n) of n-channel type MISFET is formed and a gate electrode(10p) of p-channel type MISFET is formed. A heat treatment of the semiconductor substrate is performed at a temperature of 700 degrees centigrade or higher temperature.

机译：目的：提供一种制造半导体集成电路器件的方法和由此制造的半导体集成电路器件，以抑制杂质在布置在n沟道型MISFET和p沟道型MISFET之间的边界附近的栅电极中的相互扩散。组成：栅极绝缘层（6a，6b）形成在半导体衬底（1）的主表面上。在其上形成硅层。将多种杂质引入到硅层中，从而硅层的一部分形成为n型硅层，而另一部分形成为p型硅层。在n型硅层和p型硅层的每一个之上形成包含钨或硅化钨作为主要成分的导电层。对导电层，n型硅层和p型硅层进行构图，从而形成n沟道型MISFET的栅电极（10n），并形成p沟道型MISFET的栅电极（10p）。形成。半导体衬底的热处理在700摄氏度或更高的温度下执行。

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公开/公告号KR20040104404A

专利类型
公开/公告日2004-12-10

原文格式PDF
申请/专利权人 RENESAS TECHNOLOGY CORP.;
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申请/专利号KR20040038660
发明设计人 ASAKA KATSUYAKI;HASEGAWA MASATOSHI;MATSUMOTO DAICHI;MORI KAZUTAKA;SAKAI SATOSHI;
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申请日2004-05-29
分类号H01L21/8238;
国家 KR
入库时间 2022-08-21 22:06:25

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