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3-transistor OTP ROM using CMOS gate oxide antifuse

机译:使用CMOS栅极氧化物反熔丝的3晶体管OTP ROM

摘要

The present invention relates to an OTP ROM using a CMOS gate oxide antifuse. According to an embodiment of the present invention, in an OTP ROM cell having a first input terminal, a second input terminal and a third input terminal, wherein the OTP ROM stores data by means of a voltage applied to the first to third input terminals, the OTP ROM cell includes a cell access transistor having a gate and drain forming the second input terminal and a source forming the first input terminal, wherein the cell access transistor is activated by a voltage applied to between the gate and source, a high-voltage blocking transistor having a gate, a drain and a source connected to the drain of the cell access transistor, wherein the high-voltage blocking transistor allows the current to flow from the drain to the source by means of a bias voltage applied to the gate, thus blocking the high voltage applied to the third input terminal from being directly applied to the cell access transistor, and an antifuse transistor having a gate forming the third input terminal, and source and drain both of which are connected to each other and are then connected to the drain of the high-voltage blocking transistor, wherein a high voltage is applied to the third input terminal and if the cell access transistor is activated, gate oxide is broken and shorted.
机译:本发明涉及使用CMOS栅氧化物反熔丝的OTP ROM。根据本发明的实施例,在具有第一输入端子,第二输入端子和第三输入端子的OTP ROM单元中,其中,OTP ROM通过施加到第一至第三输入端子的电压来存储数据,该OTP ROM单元包括单元访问晶体管,该单元访问晶体管具有形成第二输入端子的栅极和漏极以及形成第一输入端子的源极,其中该单元访问晶体管被施加在栅极和源极之间的电压,高电压激活。阻挡晶体管,其栅极,漏极和源极连接到单元访问晶体管的漏极,其中高压阻挡晶体管通过施加到栅极的偏置电压使电流从漏极流向源极,因此,阻止了施加到第三输入端子的高压直接施加到单元存取晶体管,以及具有形成第三输入端子的栅极的反熔丝晶体管和源极a。漏极和漏极都彼此连接,然后连接至高压阻挡晶体管的漏极,其中向第三输入端子施加高电压,如果激活了单元访问晶体管,则栅极氧化物会被破坏,短路。

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