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Parallel prefix networks that make tradeoffs between logic levels, fanout and wiring racks
Parallel prefix networks that make tradeoffs between logic levels, fanout and wiring racks
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机译:并行前缀网络可在逻辑级别,扇出和接线架之间进行权衡
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摘要
One embodiment of the present invention provides a circuit that performs a prefix computation. This circuit includes an N-bit prefix network comprised of prefix cells arranged into L+l logic levels, wherein the prefix network computes N outputs {YN, . . . , Y1} from N inputs {XN, . . . , X1} using an associative two-input operator ∘, such that, Y1=X1, Y2=X2∘X1, Y3=X3∘X2∘X1, . . . , and YN=XN∘XN−1 ∘X2∘X1. Within this prefix network, each prefix cell has a fanout of at most 2f+1, and there are at most 2t horizontal wiring tracks between each logic level. Additionally, l+f+t=L−1, and unlike existing prefix circuits, l0, f0, and t0.
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机译:本发明的一个实施例提供了一种执行前缀计算的电路。该电路包括由布置成L&l逻辑级的前缀单元组成的N位前缀网络,其中该前缀网络计算N个输出。 。 。 ,Y 1 Sub>&rcub;来自N个输入&lcub; X N Sub>,。 。 。 ,X 1 Sub>&rcub;使用关联的两输入运算符&compfn;,使得Y 1 Sub>&equals; X 1 Sub>,Y 2 Sub>&equals; X 2 Sub>&compfn; X 1 Sub>,Y 3 Sub>&equals; X 3 Sub>&compfn; X 2 Sub>&compfn; X 1 Sub>,。 。 。和Y N Sub>&equals; X N Sub>&compfn; X N&minus; 1 Sub>&compfn; X 2 Sub>&compfn; X < Sub> 1 Sub>。在此前缀网络内,每个前缀单元的扇出最多为2 f Sup>&plus; 1,并且每个逻辑电平之间最多有2 t Sup>个水平布线。另外,l&f&t;等于L&-1;并且与现有的前缀电路不同,l> 0,f> 0和t> 0。
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