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HIGHER-ORDER SYNTHESIZER, MODEL CREATION METHOD FOR HARDWARE VERIFICATION, AND HARDWARE VERIFICATION METHOD

机译：高阶合成器，硬件验证的模型创建方法和硬件验证方法

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摘要

PPROBLEM TO BE SOLVED: To create a general purpose programming language model for verifying hardware in a clock cycle unit without using any HDL simulator. PSOLUTION: In a higher-order synthesizer for performing higher-order synthesizing of hardware at a register transfer level from action analysis information acquired from analysis of action description, a cycle accurate model creation part 113 creates a calculation formula for calculating a register status and a calculation formula for calculating a controller status from action information of components to which action is allocated, data path information showing connection between the components, and status transition information about a controller. A cycle accurate model is created by using the created calculation formulas as description based on a general purpose programming language for verifying hardware at a cycle accurate level. PCOPYRIGHT: (C)2005,JPO&NCIPI

机译：

要解决的问题：在不使用任何HDL模拟器的情况下，创建用于验证时钟周期单元中的硬件的通用编程语言模型。

解决方案：在用于根据从动作描述分析获得的动作分析信息以寄存器传送级别执行硬件的高阶合成的高阶合成器中，周期精确模型创建部113创建用于计算寄存器的计算公式。状态和用于根据分配了动作的组件的动作信息，表示组件之间的连接的数据路径信息以及关于控制器的状态转移信息来计算控制器状态的计算公式。通过基于通用编程语言，使用创建的计算公式作为描述来创建周期精确模型，以在周期精确级别上验证硬件。

版权：（C）2005，JPO＆NCIPI 展开▼

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公开/公告号JP2004348606A

专利类型
公开/公告日2004-12-09

原文格式PDF
申请/专利权人 SHARP CORP;
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申请/专利号JP20030147025
发明设计人 MORISHITA TAKAHIRO;ONISHI MITSUHISA;
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申请日2003-05-23
分类号G06F17/50;
国家 JP
入库时间 2022-08-21 22:28:53

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