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Generation method of design constraints for the module of an integrated circuit design a hierarchical system
Generation method of design constraints for the module of an integrated circuit design a hierarchical system
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机译：分层设计集成电路设计模块的设计约束生成方法
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摘要
What is disclosed is a method for budgeting timing in a hierarchically decomposed integrated circuit design, which includes: 1) optimizing at least one path through block pins, the optimization resulting in assigned gains for all the cells along said at least one path; 2) performing timing analysis on the at least one path, the timing analysis using the assigned gains in order to generate arrival times for signals at said block pins; and 3) deriving a tinting budget by examining said generated arrival times at said block pins.
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