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Method and device for characterizing a CMOS logic cell designed to be implemented in a technology of type partially depleted silicon-on-insulator (PD-SOI)
Method and device for characterizing a CMOS logic cell designed to be implemented in a technology of type partially depleted silicon-on-insulator (PD-SOI)
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机译：用于表征设计为以部分耗尽型绝缘体上硅（PD-SOI）技术实现的CMOS逻辑单元的方法和装置
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摘要
The method comprises a modelling of the cell and a phase of determining the internal potentials (Vb) of transistors of the cell in a state of dynamic equilibrium, that is in steady state (AC), based on a functional simulation of the modelled cell by utilizing a binary stimulation signal (ST0) having an initial logic value, and on cancellation, within an error of precision, the sum of squares of variations of the quantities of charge in the floating substrates (B) of the transistors of the cell in the course of a period (P) including two successive transitions (TRn,TRn+1) of the stimulation signal. The phase of determining the internal potentials comprises, in an iterative manner and just to obtain the cancellation of the sum on one period of the stimulation signal, the functional simulation (MSIM) of the modelled cell delivering the variation of the quantities of charge in the floating substrates on the basis of the current values of the internal potentials, and an optimization treatment (MOPT) of the values of the internal potentials comprising the cancellation of an objective function equal to the sum. The method also comprises a phase of determining the potentials of the floating substrates in a state of static equilibrium (DC), and a phase of determining the difference between the speeds of evolution of the potentials of the floating substrates of the transistors with p-type channel and n-type channel of the cell between the state of static equilibrium and the state of dynamic equilibrium obtained for the stimulation signal. The internal potentials are determined after the first occurrence of the transition of the stimulation signal, and after the second occurrence of the transition of the stimulation signal; the internal potentials are determined according to the worst of the best case of the cell delay, on the basis of the internal potentials after each of the two occurrences, the internal potentials in the two states, and the difference of the evolution speeds. The cell comprises at least two complementary transistors connected to at least one input of the cell where the stimulation signal is applied. The cell comprises several pairs of complementary transistors connected to several inputs of the cell, and the stimulation signal is applied successively to each input delivered at output. The cell is decomposed into elementary cells, and the internal potentials are determined separately for each elementary cell in the state of dynamic equilibrium. The determination of the difference of the evolution speeds comprises the determination of the initial slope of a curve representing teh evolution. A device (claimed) implements the method (claimed).
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