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Semiconducting component with reduced connector-related parasitic inductance/capacitance has contact area(s) connected to connecting legs not connected to mounting plate, connected together in housing
Semiconducting component with reduced connector-related parasitic inductance/capacitance has contact area(s) connected to connecting legs not connected to mounting plate, connected together in housing
The device has a chip with contact areas on front and rear sides, a plate on which the rear side of the chip is mounted and with which a first contact area is in electrical contact, a housing exposing a side of the plate facing away from the chip and connecting legs protruding out of it. At least one leg is part of the plate. At least one contact area is connected to connecting legs unconnected to the plate but connected together in the housing. The device has a semiconducting chip (10) with first and second (13,14) contact areas on the front and rear sides, a mounting plate (30) on which the rear side of the chip is mounted and with which the first contact area is in electrical contact and a housing (20), whereby a side of the plate facing away from the chip is exposed and connecting legs (31,41,42, 52) protruding out of the housing, whereby at least one legs is part of the plate. At least one contact area is electrically connected to at least two connecting legs that are not connected to the mounting plate and are connected together in the housing.
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