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Demultiplexer arrangement e.g. for multi-scanned CDR-circuits in communication systems, uses at least one demultiplexer stage for receiving scanning values from first stages and combining them to form scanned word
Demultiplexer arrangement e.g. for multi-scanned CDR-circuits in communication systems, uses at least one demultiplexer stage for receiving scanning values from first stages and combining them to form scanned word
A demultiplexer arrangement has several first demultiplexer stages (12) to which are supplied the scanning values of a correspondingly scanned signal (RX) with a corresponding scanning clock (11). Each of the demultiplexer stages (12) has at least one clock divider (13) and circuit devices (14,15) for outputting the respective supplied scanning values (10). At least one second demultiplexer stage (not shown here) receives the scanning values (QA,QB) outputted by the first stages (12) and combines them to a scanned word (SDQ). A phase correction device (not shown) receives the divided scanned clock-pulses (CLK,CLKB) of the first demultiplexer stage (12) and is designed so that the position of the scanning phases of the divided scanned clock-pulses to one another is ascertained and generates clock signals dependent on this position for the at least second demultiplexer stage. An Independent claim is included for a CDR- circuit arrangement for clock- and data-recovery.
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