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METHOD FOR ANALYZING LOW VOLTAGE SWING BUS OF STATIC TIMING ANALYZER FOR SIMPLY AND PRECISELY VERIFYING TIMING
METHOD FOR ANALYZING LOW VOLTAGE SWING BUS OF STATIC TIMING ANALYZER FOR SIMPLY AND PRECISELY VERIFYING TIMING
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机译：静态时序分析器低压摆动母线的分析方法，用于简化时序和简化时序验证
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摘要
PURPOSE: A method for analyzing a low voltage swing bus of a static timing analyzer for simply and precisely verifying timing is provided to verify the timing simply and precisely by using a sense amplifying flip-flop modeled to have a predetermined setup time when a semiconductor circuit or logic including the low voltage swing bus is analyzed by a static timing analyzer. CONSTITUTION: A timing verifying program is executed by receiving a design file(S310). The timing of each node is calculated by extracting a timing model for respective cells in the design file from a database(S320). The timing of the nodes connected to the sense amplifying flip-flop is calculated by extracting the timing model of the sense amplifying flip-flop among the cells in the design file through a sub routine(S330). If the timing of respective cells in the design file is completely calculated, a timing result report is output(S340).
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