首页> 外国专利> Command processor for a three-dimensional graphics accelerator which includes geometry decompression capabilities and method for processing geometry data in said graphics accelerator

Command processor for a three-dimensional graphics accelerator which includes geometry decompression capabilities and method for processing geometry data in said graphics accelerator

机译:用于三维图形加速器的命令处理器,其包括几何图形解压缩能力和用于在所述图形加速器中处理几何数据的方法

摘要

A 3-D graphics accelerator which includes a command block with geometry data decompression capabilities and thus includes improved performance over prior art designs. The 3-D graphics accelerator couples to a system bus in the computer system and receives compressed geometry data from the system memory. The 3-D graphics accelerator includes a command block or preprocessor, a plurality of floating point processors or blocks, and one or more draw processors or blocks. The command processor includes a first data path which transmits non-compressed geometry data, and a second data path which receives the compressed geometry data and decompresses the compressed geometry data. In the preferred embodiment, the command processor includes one or more input buffers, a geometry decompression unit, and multiplexer logic. The input buffers couple to the system bus for receiving geometry input data. The geometry input data includes compressed geometry input data and non-compressed geometry input data. The geometry decompression unit couples to an output of the input buffers and receives and decompresses the compressed geometry input data. The multiplexer receives the non-compressed output from the input buffers and receives the decompressed output from the geometry decompression unit. The multiplexer includes an output which selectively provides either the non-compressed geometry data or the decompressed geometry input to other logic in the system.
机译:3-D图形加速器,其包括具有几何数据解压缩功能的命令块,因此与现有技术设计相比具有改进的性能。 3-D图形加速器耦合到计算机系统中的系统总线,并从系统内存中接收压缩的几何数据。 3-D图形加速器包括命令块或预处理器,多个浮点处理器或块以及一个或多个绘图处理器或块。命令处理器包括发送未压缩的几何数据的第一数据路径,以及接收压缩的几何数据并解压缩压缩的几何数据的第二数据路径。在优选实施例中,命令处理器包括一个或多个输入缓冲器,几何解压缩单元和多路复用器逻辑。输入缓冲器耦合到系统总线以接收几何输入数据。几何输入数据包括压缩的几何输入数据和非压缩的几何输入数据。几何解压缩单元耦合到输入缓冲器的输出,并接收和解压缩压缩的几何输入数据。多路复用器从输入缓冲器接收未压缩的输出,并从几何结构解压缩单元接收解压缩的输出。多路复用器包括一个输出,该输出有选择地向系统中的其他逻辑提供未压缩的几何数据或解压缩的几何输入。

著录项

  • 公开/公告号EP0817117B1

    专利类型

  • 公开/公告日2004-03-10

    原文格式PDF

  • 申请/专利权人 SUN MICROSYSTEMS INC;

    申请/专利号EP19970110798

  • 发明设计人 DEERING MICHAEL F.;

    申请日1997-07-01

  • 分类号G06T1/20;G06T9/00;

  • 国家 EP

  • 入库时间 2022-08-21 22:58:26

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