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Dynamic logic circuit with beta controllable noise margin

机译:具有beta可控噪声裕度的动态逻辑电路

摘要

A domino logic circuit has a beta controllable noise margin and an ability to hold an evaluated state until a received clock signal goes to a low state by adding an additional N-channel field effect transistor (NFET) in series with another N-channel field effect transistor, where both of these devices receive the date input signal. Additionally, a P-channel field effect transistor (PFET) also receives the data input signal into its gate electrode. This P-channel field effect transistor is positioned so that it opposes one of the N-channel field effect transistors. The advantages gained by this additional circuitry may also be implemented within a multiplexer circuit.
机译:多米诺逻辑电路具有beta可控的噪声容限,并且能够通过添加与另一个N沟道场效应串联的附加N沟道场效应晶体管(NFET)来保持评估状态,直到接收到的时钟信号变为低电平为止。晶体管,这两个器件都接收日期输入信号。此外,P沟道场效应晶体管(PFET)还将数据输入信号接收到其栅极中。定位该P沟道场效应晶体管,使其与N沟道场效应晶体管之一相对。通过该附加电路获得的优点也可以在多路复用器电路中实现。

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