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Sigma-delta programming device for a PLL frequency synthesizer, configuration using the sigma-delta programming device, PLL frequency device, and method for programming a programmable device
Sigma-delta programming device for a PLL frequency synthesizer, configuration using the sigma-delta programming device, PLL frequency device, and method for programming a programmable device
A sigma-delta programmer is supplied with a data word having a word length of N bits. The most significant L bits of the data word represent the places before the decimal point, and the remaining NL less significant bits represent the places after the decimal point in the data word. A sigma-delta modulator is supplied with the NL1 less significant bits of the data word. An adder receives the L1 most significant bits of the data word and a data word that is output by the sigma-delta modulator, and outputs a signal, which is multiplied by the value two by a multiplier.
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