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Double width data bus, single rate to single width data bus, double rate converter circuit
Double width data bus, single rate to single width data bus, double rate converter circuit
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机译：双倍宽度数据总线，单倍率到单倍宽度数据总线，双倍率转换器电路
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摘要
A converter circuit for converting a double width data bus (transmitting data at a single rate) to a single width data bus (transmitting data at a double rate). The circuit operates with a single clock, using the clock (positive clock) and its complement phase (negative clock) to process a set of even data and odd data. The circuit has a data mixer stage and an XOR stage. Even and odd data are mixed, using multiplexors and the positive and negative clocks, to generate mixed data. An XOR function is performed on the mixed data, using NAND gates. Using NAND gates to perform the XOR instead of a multiplexor ensures synchronous output timing, and ensures that the two stages are fully testable according to any scan-chain test method.
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