A method of optimizing high performance integrated CMOS circuit designs for power consumption and speed using global and greedy optimizations in combination

• 1. 一种可优化功耗的纳米CMOS电路容错映射方法 [P] . 中国专利： CN113343614A . 2021-09-03
• 2. 一种提升高性能集成电路产出的速度分级优化结构及方法 [P] . 中国专利： CN106326535B . 2019.08.06
• 3. Method of optimizing high performance CMOS integrated circuit designs for power consumption and speed using global and greedy optimizations in combination [P] . 美国专利： US6785870B2 . 2004-08-31

  机译： 结合全局和贪婪优化，针对功耗和速度优化高性能CMOS集成电路设计的方法

• 4. Method of optimizing high performance CMOS integrated circuit designs for power consumption and speed using global and greedy optimizations in combination [P] . 美国专利： US2003177452A1 . 2003-09-18

  机译： 结合全局和贪婪优化，针对功耗和速度优化高性能CMOS集成电路设计的方法

• 5. Method of optimizing high performance CMOS integrated circuit designs for power consumption and speed through genetic optimization [P] . 美国专利： US6711720B2 . 2004-03-23

  机译： 通过遗传优化为功耗和速度优化高性能CMOS集成电路设计的方法

• 1. New Design Methodologies for High Speed Low-Voltage 1-Bit CMOS Full Adder Circuits [J] . Subodh Wairya, Rajendra Kumar Nagaria, Sudarshan Tiwari 计算机技术与应用：英文 . 2011,第003期
• 2. Power consumption optimization methodology (PCOM) for low-power/ low-voltage 32-bit microprocessor circuit design via MTCMOS [C] . Hsu C.B., Kuo J.B. IEEE International Midwest Symposium on Circuits and Systems . 2014
• 3. Design and optimization of configurable passive components for CMOS millimeter-wave integrated circuits [D] . Liu, Gui 2011
• 4. Small-Tip-Angle Spokes Pulse Design Using Interleaved Greedy and Local Optimization Methods [O] . William A. Grissom, Mohammad-Mehdi Khalighi, Laura I. Sacolick, -1
• 5. A methodology for automated design and implementation of complex analog and digital CMOS integrated circuits applying a genetic algorithm and a CAD tool for multiobjective optimization. [O] . Pereira-Arroyo Roberto 2014
• 6. Complementary-Symmetry/Metal Oxide Semiconductor (CMOS) Circuit Hardening. Volume II. Silicon-on-Sapphire (SOS) Circuit Design Optimization and Radiation Effect Studies. [R] . phillips, d. h. pancholy, r. k. 1975

• 1. High-Speed,High-Power Motor Design for a Four-Legged Robot Actuator Optimized using the Weighted Sum and Response Surface Methods [J] . Tae-Woo Lee ,Do-Kwan Hong ,Tae-Uk Jung . 中国电工技术学会电机与系统学报(英文) . 2021,第3期
• 2. Low Power Design of High Speed CMOS Pulse Stream Neuron Circuit [J] . 陈继伟 ,石秉学 . 半导体学报：英文版 . 2000,第11期
• 3. Algorithmic Optimization of BDDs and Performance Evaluation for Multi-level Logic Circuits with Area and Power Trade-offs [J] . Saurabh Chaudhury ,Anirban Dutta . 电路与系统（英文） . 2011,第3期
• 4. A New Method for Optimizing Layout Parameter ofan Integrated On-Chip Inductor in CMOSRF IC's [J] . 李力南 ,钱鹤 . 半导体学报：英文版 . 2000,第12期
• 5. 降低CMOS电路测试功耗的方法比较 [C] . 骆祖莹 ,闵应骅 ,杨士元 . 第九届全国容错计算学术大会 . 2001
• 6. 模数混合信号电路测试的低功耗设计优化方法研究 [A] . 冯兵 . 2012