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A Digital Block Design Of Bus Arbitration In IEEE1394 Transceiver
A Digital Block Design Of Bus Arbitration In IEEE1394 Transceiver
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机译：IEEE1394收发器中总线仲裁的数字模块设计
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摘要
PURPOSE: A method for digitally embodying a bus arbitration in an IEEE 1394 transceiver is provided to maintain compatibility with a conventional reference through a decoding algorithm using only "0" and "1" when performing a bus automatic configuration and the bus arbitration, reduce a size of a logic circuit, and prevent an operation error. CONSTITUTION: When reconfiguring a system, an automatic configuration process of the system is started through a bus reset process. Each of nodes is configured as a topology with a tree structure, and a root is determined. A physical ID is added for identifying configurations using the tree topology. A node which transmits data through a bus obtains a use right of the bus.
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