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Sensing speed control circuit for controlling operation speed of sense amplifier and semiconductor memory device including the same
Sensing speed control circuit for controlling operation speed of sense amplifier and semiconductor memory device including the same
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机译：用于控制感测放大器的操作速度的感测速度控制电路以及包括该感测速度控制电路的半导体存储装置
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摘要
PURPOSE: A sensing speed control circuit capable of controlling an operation speed of a sense amplifier and a semiconductor memory apparatus having the sensing speed control circuit are provided to test a characteristics of a sense amplifier by dropping the operation speed of the sense amplifier in a test mode. CONSTITUTION: A memory cell array(11) includes a control circuit for reading and writing data in plural memory cells and a sense amplifier. An instruction decoder(12) decodes an instruction(CMD) having a packet form applied from an outside to generate plural control signals(BSEN,CNT1,CNT2,CNT3). An address decoder(13) decodes an address applied from an outside to generate a signal(WL-EN) for enabling a word line of the memory cell array(11). A sensing speed control circuit(100) includes a test register(14), a speed control circuit(15), and a sense amplifier control circuit(16). A delay locked loop circuit(17) does not operate if the second control signal(CNT2) is activated, and otherwise, if the third control signal(CNT3) is activated, it operates.
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