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LAYOUT STRUCTURE OF HIGH-SPEED RAMBUS DRAM CAPABLE OF REDUCING CHIP SIZE
LAYOUT STRUCTURE OF HIGH-SPEED RAMBUS DRAM CAPABLE OF REDUCING CHIP SIZE
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机译：减小芯片尺寸的高速RAMBUS DRAM的布局结构
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摘要
PURPOSE: A layout structure of a high-speed Rambus DRAM is provided to be capable of reducing an overall chip size by arranging a packet decoding logic between a DLL circuit region and a packet command input circuit region. CONSTITUTION: A packet decoding logic circuit region(200) is partially arranged between a DLL circuit region(100) and a packet command input circuit region. A part of the packet decoding logic circuit region(200) is an RQ packet decoding block. The RQ decoding block parses a packet command received through an RQ input receiver of the packet command input circuit region, and generates an internal control signal, which is synchronized with a clock signal of 400MHz from the DLL circuit region(100).
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