首页> 外国专利> Chopper comparator showing high speed and low power operations free of malfunction under variation of logical threshold voltage of invertor

Chopper comparator showing high speed and low power operations free of malfunction under variation of logical threshold voltage of invertor

机译:斩波比较器在逆变器逻辑阈值电压变化的情况下显示出高速和低功率运行而无故障

摘要

The present invention also provides a chopper comparator for comparing an analog input signal voltage (Vin) and a comparative reference voltage (Vref). The chopper comparator comprises the following elements. First and second input terminals (8, 9) are provided for receiving the analog input signal voltage (Vin) and the comparative reference voltage (Vref) respectively. A first capacitance (C1) is provided which has a first input side terminal being connected through a first switch (1) to the first input terminal (8). A second capacitance (C2) is provided which has a second input side terminal being connected through a second switch (2) to the second input terminal (9). A data latch circuit (12) is provided which is connected to first and second output terminals of the first and second capacitances (C1, C2). A third switch (3) is provided between the first and second input side terminals of the first and second capacitances (C1, C2), wherein after the first and second switches (1, 2) have turned OFF to discontinue applications of the analog input signal voltage (Vin) and the comparative reference voltage (Vref) to the first and second capacitances (C1, C2) respectively, then the third switch (3) turns ON to form a short circuit between the first and second input side terminals of the first and second capacitances (C1, C2).
机译:本发明还提供一种斩波比较器,用于比较模拟输入信号电压(Vin)和比较参考电压(Vref)。斩波比较器包括以下元件。提供第一和第二输入端子(8、9)以分别接收模拟输入信号电压(Vin)和比较参考电压(Vref)。提供第一电容(C1),其具有通过第一开关(1)连接到第一输入端子(8)的第一输入侧端子。提供第二电容(C2),其具有第二输入侧端子,该第二输入侧端子通过第二开关(2)连接到第二输入端子(9)。提供了数据锁存电路(12),其连接到第一和第二电容(C1,C2)的第一和第二输出端子。在第一和第二电容(C1,C2)的第一和第二输入侧端子之间提供第三开关(3),其中在第一和第二开关(1、2)已经断开以中止模拟输入的施加之后信号电压(Vin)和比较参考电压(Vref)分别施加到第一和第二电容(C1,C2),然后第三开关(3)导通,从而在第一和第二输入侧端子之间形成短路第一和第二电容(C1,C2)。

著录项

  • 公开/公告号EP0831592B1

    专利类型

  • 公开/公告日2003-03-26

    原文格式PDF

  • 申请/专利权人 NEC CORP;

    申请/专利号EP19970250284

  • 发明设计人 KURAUCHI AKIRA;YUKAWA AKIRA;

    申请日1997-09-20

  • 分类号H03M1/00;H03K5/24;

  • 国家 EP

  • 入库时间 2022-08-21 23:54:01

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