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SYSTEM FOR MODELING A PROCESSOR-ENCODER INTERFACE BY COUNTING NUMBER OF FAST CLOCK CYCLES OCCURING IN ONE SLOWER CLOCK CYCLE AND TRIGGERING A DOMAIN MODULE IF FAST CLOCK REACHES THE CORRESPONDING NUMBER OF CYCLES
SYSTEM FOR MODELING A PROCESSOR-ENCODER INTERFACE BY COUNTING NUMBER OF FAST CLOCK CYCLES OCCURING IN ONE SLOWER CLOCK CYCLE AND TRIGGERING A DOMAIN MODULE IF FAST CLOCK REACHES THE CORRESPONDING NUMBER OF CYCLES
An interface is provided between a digital signal processor or the like and an output encoder or the like that is capable of counting a system clock of the digital signal processor, generally having a higher clock rate, with respect to at least one or more clocks generally having a lower clock rate. The digital signal processor system clock is passed to the interface that has at least one or more counters. When the accumulation of the system clock reaches a corresponding number of the other clocks, a domain module in the output encoder is triggered, and the corresponding clock counters are reset. The interface may be implemented as a software modeling routine suitable for utilization by a digital signal processor simulator to facilitate complete whole cycle simulation in which multiple clocks having various clock rates may be simulated and compared with a behavior reference. The interface provides cycle-by-cycle comparison of the clocks in an asynchronous domain. The output encoder may be compliant with an International Elector-technical Commission standard such as an audio encoder standard.
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