首页> 外国专利> METHOD AND CIRCUIT FOR INCLUDING PARITY BITS IN WRITE DATA OF A MASS DATA STORAGE DEVICE, OR THE LIKE, USING A 48/54 MTR (3:K) CODE CONSTRAINT, AND POST-PROCESSING CIRCUIT AND METHOD FOR PROCESSING READ BACK DATA THAT INCLUDES SAID CODE CONSTRAINT

METHOD AND CIRCUIT FOR INCLUDING PARITY BITS IN WRITE DATA OF A MASS DATA STORAGE DEVICE, OR THE LIKE, USING A 48/54 MTR (3:K) CODE CONSTRAINT, AND POST-PROCESSING CIRCUIT AND METHOD FOR PROCESSING READ BACK DATA THAT INCLUDES SAID CODE CONSTRAINT

机译：方法和电路，用于使用48/54 MTR（3：K）代码约束将奇偶校验位写入大量数据存储设备或类似数据的写入数据中，以及用于处理回读数据（包括所述数据）的后处理电路和方法代码约束

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摘要

A method for writing data to a mass data storage device (10) includes applying a maximum transition run length code constraint to the data to be written, generating parity data based on the data, and inserting the parity data into the data to be written (5A-C). The parity data is used in conjunction with a post-processor (66) to detect and correct errors in the read back data.

机译：一种将数据写入海量数据存储设备（ 10 ）的方法，包括对要写入的数据施加最大过渡游程长度代码约束，基于该数据生成奇偶校验数据，以及插入奇偶校验数据写入要写入的数据（ 5 AC）。奇偶校验数据与后处理器（ 66 ）结合使用，以检测和纠正回读数据中的错误。 展开▼

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公开/公告号US6581184B1

专利类型

公开/公告日2003-06-17

原文格式PDF

申请/专利权人 TEXAS INSTRUMENTS INCORPORATED;
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申请/专利号US20000547387

发明设计人 KOSHIRO SAEKI;MICHAEL J. PALMER;
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申请日2000-04-11

分类号H03M130/00;G06F110/00;

国家 US

入库时间 2022-08-22 00:06:52

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