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Flowgraph representation of discrete wavelet transforms and wavelet packets for their efficient parallel implementation

机译:离散小波变换和小波包的流程图表示,以实现高效的并行实现

摘要

The invention relates to a microprocessor structure for performing a discrete wavelet transform operation. It uses a flowgraph representation of discrete wavelet transforms (DWTs) and wavelet packets. This representation is useful for developing efficient parallel algorithms and VLSI architectures. As examples, two DWT architectures for Haar wavelets and three architectures for Hadamard wavelets and wavelet packets are proposed with the efficiency (counted as the measure of the average utilization of basic processing elements) of approximately 100%. The proposed architectures are fast and provide excellent performance with respect to area-time characteristics. They are scalable, simple, regular, and free of long connections (depending on the length of input signal). The invention can be extended to inverse wavelet transforms.
机译:本发明涉及用于执行离散小波变换操作的微处理器结构。它使用离散小波变换(DWT)和小波包的流程图表示。此表示对于开发有效的并行算法和VLSI架构很有用。作为示例,提出了两种用于Haar小波的DWT架构以及三种用于Hadamard小波和小波包的架构,其效率(作为对基本处理元素平均利用率的度量)约为100%。所提出的体系结构是快速的,并且提供了关于时域特性的出色性能。它们具有可扩展性,简单性,规则性,并且没有长连接(取决于输入信号的长度)。本发明可以扩展到逆小波变换。

著录项

  • 公开/公告号US2003046322A1

    专利类型

  • 公开/公告日2003-03-06

    原文格式PDF

  • 申请/专利权人 GUEVORKIAN DAVID;

    申请/专利号US20020155944

  • 发明设计人 DAVID GUEVORKIAN;

    申请日2002-05-24

  • 分类号G06F17/14;

  • 国家 US

  • 入库时间 2022-08-22 00:07:23

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