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Flowgraph representation of discrete wavelet transforms and wavelet packets for their efficient parallel implementation
Flowgraph representation of discrete wavelet transforms and wavelet packets for their efficient parallel implementation
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机译:离散小波变换和小波包的流程图表示,以实现高效的并行实现
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摘要
The invention relates to a microprocessor structure for performing a discrete wavelet transform operation. It uses a flowgraph representation of discrete wavelet transforms (DWTs) and wavelet packets. This representation is useful for developing efficient parallel algorithms and VLSI architectures. As examples, two DWT architectures for Haar wavelets and three architectures for Hadamard wavelets and wavelet packets are proposed with the efficiency (counted as the measure of the average utilization of basic processing elements) of approximately 100%. The proposed architectures are fast and provide excellent performance with respect to area-time characteristics. They are scalable, simple, regular, and free of long connections (depending on the length of input signal). The invention can be extended to inverse wavelet transforms.
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